Conventionally, in integrated circuits (semiconductor devices) with high packaging density, elements are arranged closely and in some cases a plurality of resistors or MOS transistors may be arranged close to a capacitor. When a capacitor, resistors and MOS transistors are arranged in a dense layout, they are formed in a process shown in FIGS. 6 and 7, for example. More specifically, a field oxide film 2 is formed to cover an area A.sub.R for forming resistors R and an area A.sub.C for forming a capacitor C, while a gate oxide film 3 is formed with a thickness of about 250 (.ANG.) in an area A.sub.TR for forming MOS transistors TR, and then a polysilicon film 4, a capacitor-dielectric/insulating film 5 and a polysilicon film for an upper electrode are formed on the field oxide film 2 and the gate oxide film 3. After a mask pattern is formed on an area where the upper electrode of the capacitor C is to be formed, the upper electrode 7 is formed by etching the polysilicon film for the upper electrode.(FIG. 6(a)).
Subsequently, a CAP oxide film 10 and a resist film 11 are deposited (FIG. 6(b)), then a resist pattern 11a is formed which is used to form the resistors R and the capacitor C from the resist film 11 by a photolithographic process (FIG. 6(c)), and by using this resist pattern as a mask, a mask pattern 12 for forming the resistor R and the capacitor C is formed by etching the CAP oxide film 10 (FIG. 6(d)).
Next, a tungsten silicide film 13 and a CAP oxide film 15 are deposited, and a resist film 16 is formed (FIG. 6(e)). A resist pattern 16a for forming the gate electrodes of the MOS transistors TR is formed from the resist film 16 by a photolithographic process (FIG. 7(a)), and by using this resist pattern as a mask, a mask pattern 17 for forming the gate electrodes is formed by etching the CAP oxide film 15, and then the resist pattern 16a is removed (FIG. 7(b)).
When the tungsten silicide film 13 is etched away by using the mask pattern 17 for forming the gate electrodes as an etching mask and the mask pattern 12 for forming the resistors R and the capacitor C is exposed, the polysilicon film 4 is etched away by using this mask pattern 12 and also the mask pattern 17 for forming the gate electrodes (FIG. 7(c)). An LDD forming oxide film by which to form an LDD structure is formed, and the LDD forming oxide film is etched anisotropically to form side-walls (FIG. 7(d)), finally a thin oxide film is formed on the exposed silicon substrate 1 by heat treatment in an oxidizing atmosphere, and this thin oxide film is shaped into a mask for ion implantation to form source and drain diffused regions (FIG. 7(e)).
Thus, a plurality of resistors R, a capacitor C and a plurality of gate electrodes TR-G have been formed. By diffusing impurities into the active region by using the gate electrodes TR-G and the side-walls 18 as masks, a plurality of transistors TR are formed each having source and drain diffused regions of the LDD structure in which the source and drain are of dual structure.
However, in the above-mentioned conventional method, there are a difference in height between the capacitor C and the resistors R and another difference in height between the capacitor C and the MOS-transistor gate electrodes TR-G. Therefore, the thickness of the resist film is uneven in the resistor-forming area A.sub.R and the transistor-forming area A.sub.TR, with the result that the resist film differs in thickness between at a part .alpha. near the capacitor C and at a part .beta. away from the capacitor C. Consequently, in the exposure step in the formation of the resist pattern, light intensity acting on the resist film differs between at the part .alpha. and at the part .beta. of the resist film owing to the standing-wave effect. For this reason, there is a possibility that resistors R or gate electrodes TR-G designed with the same width on a reticle are formed with difference widths in the patterned resist.
If the width differs among resistors R or among gate electrodes TR-G, this causes differences in resistance value among the resistors R designed to have the same resistance value and also leads to differences in characteristics among MOS transistors designed to have identical characteristics, and thus a problem of lowering of analog characteristics arises.
A possible way of suppressing variations in light intensity owing to the standing-wave effect by reducing the thickness variation of the resist film is to dispose the resistors R and the MOS transistors TR in positions remote from the capacitor C. However, this method is not preferable because it increases the chip area and leads to a decrease in the component packaging density.
In the step of FIG. 7(e), after the side-walls 18 have been formed by anisotropic etching, a thin oxide film is formed in the exposed surfaces of the silicon substrate 1 by heat treatment in an oxidizing atmosphere. In this heat treatment, those parts of the polysilicon film 4 which are to become the resistors R are also oxidized because those parts are exposed to the oxidizing atmosphere. For reasons such as the uneveness of the thickness of the oxide film above the resistors R after the side-walls for forming the LDD structure have been formed, if in a wafer or in a chip there is variation in diffusion level of oxygen as the oxidizing gas, this results in variation in the thickness of the polysilicon film 4 and also in the resistance value among the resistors R designed to have identical characteristics, which has been a problem.
Problems with the capacitor C are that the etching step carried out to form the upper electrode 7 causes damage to the capacitor-dielectric/insulating film 5 near the edge of upper electrode 7 and in some cases causes a current to leak between the upper electrode 7 and the polysilicon film 4 as the lower and upper electrodes of the capacitor due to the electric field concentration at the lower side edge of the upper electrode 7.
The present invention has been made with those conventional, unsolved problems taken into consideration. The present invention has as its object to form a resistor or a MOS transistor that have characteristics as designed in a semiconductor device in which a capacitor and a resistor or a MOS transistor are arranged.